The present invention relates a flash memory device. More particularly, the present invention relates to substrates in a flash memory device.
A flash memory device is a type of EEPROM (electrically erasable programmable read only memory) and is fast becoming a common device to store information. Today""s flash memory devices are being used in numerous electronic devices including, but not limited to, digital cameras, MP3 players, laptop computers, personal digital assistants (PDAs), video game consoles, and the like. It is noted that numerous printers, e.g., inkjet, laser, and dedicated photograph printers are also being configured with flash memory drives to read flash memory devices. A flash memory device provides both the speed of volatile memory (RAM-random access memory) and the data retentive qualities of non-volatile memory (ROM.-read only memory). Additionally, with continued miniaturization of components and circuitry within an electronic system, flash memory devices are well suited to be incorporated into the diminutively sized systems.
As flash memory technology progresses, increased memory density and speed become critical. Writing to a flash memory cell and erasing a flash memory cell are slow when compared to reading of a flash memory cell. To read a cell, it is necessary to ensure that the drain current (also the reading current of the cell) is large enough to drive the output and to be able to control the level of the drive output buffer and speed. The speed with which the cell is read is determined by several factors including, but not limited to, the channel length of the device, e.g., a MOSFET (metal oxide semiconductor field emitting transistor), the threshold voltage, and gate oxide thickness.
To provide additional speed, the channel length has been continuously decreased to increase density and drive current for improved core gain, thus increasing speed of the device. However, there is a fundamental limit on the gate oxide or tunnel oxide thickness for flash memory due to reliability reasons. The tunnel oxide can not be scaled aggressively thin by virtue of the high voltage operations it undergoes during writing (programming) and erasing. This limits the core gain as the device is scaled down in terms of channel length.
Further, to comply with new diminutive form factors and other reduced size requirements, scaling down (size reduction) of the flash memory device is not without shortcomings. Scaling down of a flash memory device can cause problems with the internal effects of the flash memory device, e.g., degradation of the drive current, arising because of serious resistance from substrate doping problems.
Doping problems can include not driving the dopant deep enough into the substrate, or driving the dopant too deep into the substrate. Other problems can include having an excessively concentrated dopant, and conversely, having an insufficiently concentrated dopant. The amount of dopant concentration affects the operation of the transistor and, accordingly, the flash. memory device.
The dopant concentration is even more critical as flash memory devices become smaller and smaller and channel length decreases and where increased speed is demanded. A higher concentration of dopant will increase the Vt (threshold voltage) of the transistor while reducing associated leakage, which unfortunately reduces the speed at which the transistor can operate. The leakage is between the source and drain of the transistor. Additionally, if the dopant concentration is too high, thus a high Vt, a greater Vg (gate voltage) is required to provide enough overdrive to overcome the higher Vt and enable reading of the cell.
A lower concentration of dopant increases the speed with which the transistor can operate. It is noted, however, that a lower concentration of dopant will alsodecrease the Vt of the transistor and, unfortunately, increase associated leakage between the source and the drain. Further, because of the increase in leakage between the source and the drain, transistor functionality and reliability can be adversely affected with a dopant having too low of a concentration.
Thus, a need exists for a method to increase the speed in which a flash memory device is read. Another need exists for a method that increases core gain while maintaining a dopant concentration that provides the lowest threshold voltage and the least amount of leakage between the source and the drain. Yet another need exists for a method that increases core gain in a flash memory device while retaining device functionality and reliability.
Embodiments of the present invention are drawn to providing a method and apparatus for a memory device, e.g., a flash memory device, with increased core gain, through the formation and utilization of strained silicon. The present invention further provides a method and apparatus for a memory device which achieves a reduction in electron scattering. The present invention further provides a method and apparatus for a memory device that achieves the above and which is readily implementable in a memory device fabrication process.
A method of memory device fabrication is described. In one embodiment, the method of memory device fabrication comprises implanting an element in a substrate. The element causes an inherent elongational realignment of atoms in silicon when silicon is formed upon the substrate when the element is implanted therein. A layer of silicon is then formed on the substrate having the element implanted therein. The alignment of atoms of the silicon elongates to an atomical alignment equivalent to that of the element. The layer of silicon and the substrate are then crystallized, subsequent to the elongational realignment of atoms of said layer of silicon, wherein a crystallized layer of elongated silicon decreases electron scattering thus realizing increased core gain in the memory device. In one embodiment, the element implanted in the substrate is germanium.